Kioxia's guidance missed expectations! What lies ahead for the memory chip sector?
美光科技 技术网络研讨会
Key Takeaways (AI-Generated)
Business Highlights
- Micron is in high-volume manufacturing with HBM4, moving to HBM4E, and developing Vertical HBM for direct integration on processing units.
- DRAM scaling continues with 1-gamma; 1-delta node ramps in H2 2027 with mid-20s% bit density improvement. Planar scaling extends to 1-zeta before 3D transition.
- Gen 11 NAND doubles bit density vs Gen 9, targets 1.5x I/O speed, and uses wafer-to-wafer bonding, ramping in H2 2027.
- LPDDR6 offers 35% better power efficiency than LP5. DDR6 provides 2x bandwidth of DDR5. A world-first 512GB DDR5 RDIMM was sampled.
Financial Guidance
- The 1-delta DRAM node and Gen 11 NAND are both targeted to ramp into volume production in the second half of 2027.
- Management expects memory supply to remain short relative to demand for at least the next two years, with no period of balance anticipated.
Opportunities
- Developing disruptive technologies like Vertical HBM, 3D DRAM, and AI-class NAND to meet specific AI workload requirements for bandwidth and power.
- Implementing AI tools across development accelerates execution, achieving 2x faster silicon-to-tape-out for SSD controllers and 60% less time for full product development.
- Deepening co-innovation partnerships with hyperscalers like Meta and startups like Weka aligns product roadmaps with customer system architectures.
- Capitalizing on the shift from training to inference and agentic AI drives higher memory content per system, expanding edge applications.
Full Transcript (AI-Generated)
Operator
After today's prepared remarks, we will host a question and answer session. If you would like to ask a question, please press *1 to raise your hand. To withdraw your question, please press *1 again. I will now hand the conference over to Satya Kumar, Corporate Vice President, Investor Relations and Treasury. Satya, please go ahead.
Satya Kumar
Thank you, Christine, and welcome to Micron Technology's webinar on technology and products leadership for the AI era and beyond. On the call with me today is Doctor Scott de Boer, President and Chief Technology and Products Officer. AI is driving significant changes in memory and storage requirements and we're excited to have Scott here with us today to provide investors a deeper look at our technology, road map and innovation strategy.
Before we begin, I want to remind everyone that today's discussion includes forward-looking statements including regarding our technology and product road maps, investments in business opportunities. These statements are subject to risks and uncertainties that could cause actual results to differ materially. Please refer to our SEC filings for a discussion of these risks. With that, let me turn it over to Scott.
Scott de Boer
All right, thanks, Satya, and good morning, everyone. Thanks for joining us today for this pivotal moment in our industry where AI is really changing so rapidly and redefining computing. Today, I'm going to talk about how Micron is shaping that future and making it real at scale. The next era of AI will definitely be driven by advancing memory storage and compute together and Micron is in a unique and strong position leading in bandwidth capacity, power efficiency, reliability and increasingly focused on supporting our customers to execute their extremely complex systems going forward.
So today I'm going to talk on a number of points and try to give you a feel for how Micron is positioned. And definitely we are in an unprecedented position in time with an opportunity for memory and storage in particular. And through this first stage of the AI transformation, Micron has executed and delivered extremely well. Micron's technology leadership really is foundational. And I'll talk today about that foundation and how it's going to evolve through time. Truly, the differentiated industry leading products that we have today and the lab going forward are all built on a core technology leadership position. And that's a focus for Micron going forward.
In addition to the technologies that we're creating in our products, AI also accelerates our team members ability to innovate and execute and it is a major focus of Micron. And I think we are leading the industry in our implementation of AI products and technology capabilities across our whole development road map really from starting physics through design, through ultimately reducing variation in manufacturing and using smart manufacturing across our ecosystem to ramp faster than we've ever done before. Also touched today on our longer horizon R&D investments that we're focused on to really enhance Micron's future competitiveness. We're making substantial investments and really changing the way that we're looking at longer term R&D investments from many, many aspects. And I'll give you a feel for some of the things that we're doing there.
I've said before several times and we've emphasized the Co innovation really is a key part and it's very different today than it was in the past. Micron's Co innovation with our partners, both suppliers and customers really are a core piece of how we deliver these leadership solutions and help Micron position itself with the optimal memory and storage to support our customers next generation products. All of this adds up to Micron being positioned to really extend our technology and product leadership for the next decade. And we're uniquely positioned I think with the strongest opportunity that we've ever had and probably the farthest extended road map in terms of technology and advanced products that I've ever seen in my career, truly unique in time.
So first just to touch on a few background pieces relative to where we're at today. The products that we've focused on and are underpinning Micron success up to this point really have been training focused and through the first part of this inferencing wave and really there's a wave of AI increases in memory demand that continually come at us and we're still in the early innings of the adoption and the evolution of the AI systems. And each of these is going to drive significant changes in usage and demand on the memory products, not just in terms of bits, but definitely in terms of capability and what type of products in the memory and storage area that we build. Truly interesting and unique period of time where Micron's technology leverage or technology position can be leveraged to really position the company stronger going forward.
When we look across the architecture that supports these waves of AI transformation, Micron's portfolio really goes across all of them. It goes across all of them through time with different types of products, different types of innovations that we focus on with our customers and really spans the portfolio from HBM today in terms of ultra high performance memory, evolving to custom and then future vertical HBM solutions that I'll talk about today supporting our customers needs at the very highest performance levels. In addition to that, we've seen over the past couple of years really the importance, the growing importance of high capacity DDR modules and the exceptional performance that's provided by low power DRAM in the data center. And that continues and expands through the next several years. And our focus as I'll talk about today is on making sure that the next generation of both DDR and low power DRAM modules are truly optimized for what's coming ahead in the AI world.
We've had great progress on the SSD front in terms of data center SSDs. The business and technical teams have really delivered strongly over this past couple years. And that's been noted in our earnings calls and in several other public disclosures relative to our progress on data center SSDs. Today I'm going to talk a little bit more about what's next in our focus really in enabling AI class NAND, which is higher performance, different varieties of higher performance NAND products that support opportunities that our customers are looking at in terms of leveraging that to get better and better performance out of the end systems. And finally, high capacity SSDs as we leverage our technology leadership and our cost structure, cost per bit structure of our advanced nodes, higher capacity SSDs continue to be a focus and continue to be a key important point for our data center customers.
But memory is not all just about data center and the technology and AI implementation into multiple other spaces is critically important as well. And a few of those on this slide noted in terms of autonomous vehicles, robotics and of course PCs and mobile all evolving with AI and all driving unique requirements from the memory technology. So what is great AI technology for data center may not be optimized and truly is not optimal for these other edge applications. And we're focused on new types of products across all these edge spaces and looking at the opportunities with our customers to build optimal memory across each of these different types of non data center focus areas going forward.
So if we look at that first wave, we've had tremendous success and building on core technology leadership to enable a number of industry firsts and best in class products. And these really span across the product portfolio that I mentioned on the previous slide, driving LPDDR in unique ways to have industry 1st and sole source positions with LP based products. The SOCAMM modules leveraging LPDDR, SOCAMM2 modules leveraging LPDDR have come out and really been a key driver of that part of our business. We've been a leader of course in SOCAMM2 and driven the highest densities available in the market. With that on the data center SSD side, we've leveraged our technology leadership and really a long term partnership both with customers and an internal focus with our SSD team to enable PCIe Gen6 1st in industry and deliver it into mass production. Micron's come a very long way from just four or five years ago in terms of our position in really being at the forefront of data center SSDs and that's something that we're very focused on. And I'll talk a little bit more about today how we're going to continue that path.
This slide highlights a number of other industry firsts that are of critical importance and of course HBM4 strength is one of those. And as we mentioned, we're in high volume manufacturing with HBM4 now very successful product ramp and a world class product there. And moving on to HBM4E that I'll talk about in the rest of the road map as well. And then one of the most recent accomplishments noted on this slide is our high density RDIMMs. We've sampled a 512 gigabyte DDR5 RDIMM recently. It's the world's first module of this sort with exceptional performance and positioning for high density module optimization and usage by our customers. Again, coming from a position a number of years ago where we weren't in the leadership role and have put significant focus over the last several years and making sure that every aspect of this product portfolio is intentionally positioned to take advantage of opportunities with our customers.
No question, as we look at the waves of AI coming towards us and inferencing raises the bar on memory technology and memory technology is fundamental to how AI works. And I think it's relevant here to just talk about all the touch points as we go through what happens and how memory evolves into this and engages into the ecosystem. Starting with just the example of a simple prompt and the context of information being stored in DRAM and coming from storage SSDs for that prompt holding the background information and then the LLM inference. Really reading that prompt and utilizing low power DRAM to optimize energy efficiency and working with capacity to drive the prompt into understanding what the answer is to that question. And then going through a number of calculations through the KV cache and then really having the HBM engine drive the data back and forth with the GPU to get to that answer, which is then generated one token at a time. And those tokens live in memory. And memory is the foundational piece of the ultimate performance of this system really driving and living in the memory.
So the position of memory has never been more important as it is relative to AI today. And this opportunity just keeps getting bigger as the models and the capability continue to grow. So when we look at the pieces of how memory drives and continues to scale to meet these waves of oncoming AI opportunity, we have to foundationally continue to scale memory. And I'll talk today about our confidence in continuing to be able to drive memory technology to meet this challenge. Absolutely, Micron has a history of successful scaling and I'll talk a little bit about some of the sustained technology leadership we have on the next slide. But this slide just highlights the foundation that we're building on and it is a little self-serving since 1995 is when I started at Micron. So I made the graph start in 1995, but 22 nodes of DRAM technology since 1995 to today ending in our 1-gamma node, which is a very high volume leadership node in the industry today. And we're building on that to really ramp this next generation of AI products over the next year. That'll be our main running node. And for context, this graph represents about 400X as stated here, more bits on a DRAM wafer since 1995.
When you look at this 1-gamma node, which is the workhorse of Micron on the DRAM side, now positions itself with a kind of a unique understandable explanation for how small it truly is in fitting more than 1500 capacitors across the width of a human hair on this node. Leadership, as we've talked about in multiple forums, has been sustained over the past multiple nodes. Really 4 nodes of DRAM consecutive leadership, 3 nodes of HBM generations in power leadership and NAND focusing on delivering 3 consecutive leadership nodes from G7 to G9. Today I'm going to talk about what comes after these, but this accomplishment really is a result of many focus areas across Micron of our outstanding technology and innovation team driving technology across many fronts and executing flawlessly over a number of years to position Micron with this leadership. And we absolutely don't take this leadership for granted. We're focused on making sure that this execution continues and that we truly continue to leverage this global world class team to enable leadership in DRAM, HBM and NAND going forward.
One last time, I'm going to use this slide. I've used it a couple of external events, but I really like the illustration of the pace of innovation in memory relative to other things. And as they look at a Porsche from 1995 with 270 horsepower and cost about $60,000 and had 23 miles per gallon. The illustration of what the pace of the memory industry versus the automotive industry really would be if automotive had matched the pace of the DRAM industry, this vehicle would now have about 2.7 million horsepower, cost $5 and have 23,000 miles per gallon if it were capable or if the auto industry had moved as fast as the DRAM industry. So really unique piece of how fast things move in this technology cadence across memory.
Another interesting piece here before I shift to the technology road maps is really that the piece of recognizing how outstanding the performance of HBM4 it truly is. And this just gives some context for exactly how powerful this device is, how complex this device is with one HBM4 stack now delivering 2.8 terabytes per second of bandwidth. And looking at the total Internet bandwidth in the world right now, this is like across the Internet, Google data worldwide Internet bandwidth is 282 terabytes per second total. So about 100 HBM4 stacks can match the worldwide Internet bandwidth. OK. But as we all know, memory is currently a focus. And as we've discussed, memory is at the center of AI and it is absolutely the limiter in terms of ultimate system performance and capability at this point. And we take that very seriously as memory has become the AI bottleneck, our focus on making sure that memory capability continues to evolve, memory architecture continues to evolve. Both of these things must happen and I'll talk about our road map to deliver that ultimately memory shapes AI capacity and performance and cost per token. So our focus is on working with customers to make sure that we deliver the optimal product solutions to make that happen.
So if we look at now stepping into Micron's technology position and again it really is a price of entry situation. Technology leadership is absolute absolutely underpins our ability to deliver the differentiated industry leading products. It's been core to the previous ones over the past couple of years and it will continue to be really that key techno foundation that underpins the next set of products that are coming along. So I'll step into exactly where we're going with core technology. So first just a general point on memory technology and the evolution on the DRAM side. Planar DRAM has been scaling for decades and Micron has been in a strong position. As mentioned, it is foundationally shrinking the XY dimensions of the DRAM. Of course it's a very vertical process now, so there's 3D aspects to it, but we don't call it 3D DRAM at the moment. It is just a function of making the chip, the cell smaller and smaller. DRAM is nearing atomic limits at this point. Although we have confidence in several more planar nodes, we are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view. So our intention as I'll talk more today is truly around making sure we have 3D DRAM prepared and that we'll implement it at the proper time for the market.
On the NAND side, I think everyone is familiar. The planar NAND ended scaling in around mid-2015 timeframe. Micron scaled that to about a 16 nanometer planar node before it wasn't capable of scaling any longer and successfully transitioned into 3D NAND which was a function of primarily the scaling adding more layers to 3D NAND across multiple nodes. The current industry direction and Micron's direction is scaling in both adding by adding layers but also by shrinking the cell dimensions. And that complexity will continue to provide benefits in terms of cost structure and performance over the next several nodes. And then we'll be looking at future alternatives, which I'll talk a little bit more about on some upcoming slides. But again, confidence in both the DRAM and the NAND scaling path. And I think from a visibility point of view have more confidence in the next several years of scaling on both DRAM and NAND than we have in quite some time.
On the DRAM road map, we have multiple and I'll go through the picture of exactly where we're at. As we've as I mentioned the 1-gamma node is in high volume manufacturing today at the basis of all the key products that are coming out in the next 12 months and very confident in that industry leading node. It was the node we introduced to EUV at first and that's been a successful introduction. Our manufacturing team has done an outstanding job of ramping that and leveraging that capability on our 1-delta node, which I'll talk about starting a little bit more on the next slide. That is the node that we're focused on in Boise. It'll be US manufactured as well as in other facilities. And this technology is coming along rapidly and our intention is to ramp that into volume in the second-half of next year. And then beyond that, we have a number of nodes in progress and just we'll talk a little bit about that path or 1-epsilon node leverages wafer bonding and optimizes the big growth and technology capability to deliver truly unique solutions in the AI space. And that's well under way. And then pathfinding we have going on both early development for our 1-zeta node, 1-zeta Angstrom node and our Ada Angstrom nodes. Beyond that bringing in combinations of high NA EUV, new materials and a number of other innovations to continue this planar road map successfully over a number of years. So lots of confidence, high confidence in this DRAM road map through this period of time.
For reference, we are, we have looked at and investigated 4F^2 DRAM really over the past two decades. Micron invented 4F^2 DRAM. The path with 4F^2 DRAM has always been an option through time and we've evaluated it and not pursued it due to increased complexity and cost through this past two decade period of time. But developments continued continuously through there and we've had a number of prototype products to compare through time. Two challenges are holding Micron or have convinced Micron not to go down. This one is the scaling path is not viable beyond a certain point. So there's no actual benefit to going down that path. The second piece is there's a bit of a misnomer about what actually drives the bit density per wafer on DRAM and foundationally. It's important to understand that the capacitor pitch, the capacitor size and dimensions is actually what sets the DRAM bit density, not whether it's 6F^2, 4F^2, 8F^2. Everything is optimized around the capacitor pitch. And then underneath actually you can optimize with 6F^2 or 4F^2 and fit those for a given capacitor dimension, however you'd like to. So it's really about optimizing process complexity, process margin and cost relative to a given capacitor pitch, which is the foundational element of how we built DRAM.
When we look at 3D DRAM, we have that on the road map as I mentioned and it's shown here. In between 1-zeta and 1-ada. But in reality, this is a parallel path and we'll implement it in a fashion that is ideal for cost and complexity and device performance. And the timing of it will depend on Micron business decisions are from a technology and a product point of view. It'll be ready to implement in the optimal time as we've done with previous major technology transitions. OK, a little more on our 1-delta node. This is focus in Boise today. The 5th consecutive industry leadership node is our anticipation with this ramp in 2027 second-half. A few early mentions on capability of this node. This is going to provide in the mid-20s percentage bit density improvement focused on optimizing cost while providing the densities that are required. The performance will be optimized to meet our HBM5, our vertical HBM and our vertical EAM products, which I'll talk about in more detail on some upcoming slides. This node really is optimized for AI and it's aimed to deliver the kind of power and bandwidth that is going to create those leadership products that we've done before and will enable in the future. So this ultimately is going to be a great node. The picture in the middle is a picture of the cells on this 1-delta node. And we're very, very excited about this node ramping over the next year.
When we look at besides the node itself, we look at the DRAM CMOS logic road map, which over the past several years has been what we have leveraged to create differentiated products. So when we look at DRAM CMOS, it is not one CMOS for a given node. We within a given node, for example, 1-beta, we will have multiple variations of CMOS that we will implement into specific products on that node. So optimized for LP performance or optimized for HBM performance, we'll have CMOS that meets the requirements to deliver to the specifications that our customers need. This has become a very significant focus for Micron over the past seven years in enabling the right technology for the right time. And we've gone through a number of different variations that we have capability for now. These have created from 2020 through 2030 projection will create about a 10X improvement in performance in terms of drive at a given leakage current to enable the kinds of performance that we need. So at multiple nodes of power and performance leadership and a road map that continues to deliver that through time and will become increasingly complex as we go forward with different generations of both planar high K and then 3D CMOS to support the needs.
When we look at DRAM based on this technology and the products that we are delivering in the next generation three that I want to highlight today are our LP6 for data center and mobile, which has been a major focus from our design teams doing a great job of putting together industry leading products here that lead that will leave the industry in power with 35% improved power versus LP5 and more than 35% on some densities. So big push on LP6, which is going to be a key memory type both for mobile obviously, but increasingly important for data center. On the DDR6 front, Micron's positioned to be a leader in DDR6 implementation lead partner with key customers to deliver this higher bandwidth 2X versus DDR5 that can be leveraged across data centers for servers, for server applications. So lots of focus on these transitions to LP6 and DDR6. And then in the meantime, I had mentioned the 512 gigabyte RDIMM that we announced recently the next generation will be delivering a 1TB RDIMM for the industry's highest capacity RDIMM products. So many different focus areas for specific customers across our DRAM product portfolio.
When we look at HBM, we're building on our HBM leadership through from the evolution from standard HBM like our HBM4 product today to what we've talked about in terms of custom HBM, both standard and custom will coexist in the ecosystem depending on the customers. We are focused on this Co-design element with our customers, Co-optimization with customers to implement both memory IP and logic IP into our base die to then deliver ultimate system performance with the customers who want custom. And of course we'll have high performance on standard HBM4E. Those customers that don't have custom design, as we go beyond that we're focused still on custom HBM and standard HBM, but we will add in a product focus that's very important going forward, which we call vertical HBM. This is a implementation of memory capability directly on top of processing units and is a key element of our customer partnership going forward in delivering this solution which provides ultimate bandwidth in combination with Co-design and also still utilizing HBM around the edges of in many cases of the XPU use. So supporting that execution is a number of advanced packaging innovations all required to deliver the HBM performance and the vertical HBM performance that we see as necessary with customers.
Interconnect density is really the driver of requirement and driver of many of the technology requirements. Ultimately, hybrid bonding technology is a major focus for Micron. Our capability is strong. This still needs to evolve through time to be prepared to implement it in a high volume manner, but ultimately the driver of hybrid bonding winds up being interconnect density. So the pitch of the pads in order to get bandwidth requires closer and closer connections, spacing closer and closer spacing between connections. Hybrid bonding is the solution to that technical problem in addition to the well publicized thermal benefits of hybrid bonding. Ultimately you can't build products with a certain level of bandwidth without hybrid bonding. So it's a major focus for Micron and we intend to be leaders in that space. Stacking technology is still key and ultimately there will be implementations going forward of higher and higher stacks because memory capacity does play a major role in driving token costs down and in system ultimate system optimization. So this particular picture in the middle of the slide indicates 16-high HBM stacks built both with micro bumps on the left and with hybrid bonding on the right. So different implementations of 16-high products and ultimately the hybrid bonding in this case is beneficial as mentioned for both bandwidth enablement and thermal improvement. So stacking technology continues to be a major, key, major technology capability. The Micron's focused on leading and it's in a strong position at this moment. It becomes even stronger requirement as we look to the transition or the inclusion of 3D vertical HBM integration products in terms of enabling as I mentioned the tighter interconnects and thermal management.
Thermal management becomes even more important as we look at vertical HBM products which have to be optimized around heat structure, both of the base die heat, heat flow both from the base die and from the XPU that the product is mounted on. So significant complexity requires very complex integration with our customers Co-designed and the designs have to be thermally aware. It's a key piece one example of an innovation that Micron has implemented in the future into our designs now is the heat spreader which takes a position on the HBM cube over the hottest part on the HBM base die and effectively serves as a chimney for heat from the base up past the HBM cube. So this innovation is a key piece in the positioning and the design of that innovation to cover that fire area of the base die is a key enabler. Going forward, token efficiency focus is an urgent requirement and it brings about a diversity of different types of products. And I'll hit on just a couple of these right now, but they're important ones. Both the free vertical HBM that I mentioned, the vertical edge inference memory, both have commonality in terms of structure in terms of the packaging requirements, the thermal requirements and the need to Co-design with customers.
As you look across this timeline of these products coming in, one thing to note is trade ratios continue to increase as you go from left to right. As these products come in, the trade ratios continue to be stressed in terms of the number of wafers it takes to build HBM, vertical HBM and vertical EIM relative to building standard DRAM bits so that pressure remains through this road map. When you look at the different packaging requirements for vertical edge inference memory versus vertical HBM, while the structure looks similar in terms of the packaging capability needed, the products are optimized in different ways where vertical EIM has lower bandwidth requirements but substantially more sensitive to power requirements. So it's really designed in a way to get bandwidth capability to drive these edge products in an effective way, but optimized for power. While vertical HBM as it is implemented in parallel with other varieties of HBM, it comes in with huge bandwidth benefits. So it's very bandwidth focused and improves in capacity over time, but really bandwidth focused is the deliverable of the vertical HBM technology.
I'm going to shift over to NAND. NAND we've been in a very strong position with our Gen 9 NAND and this leadership is going to extend with generation 11. And this is a significant leap. We have optimized this memory. We've actually gone back and ensured that this memory is optimized for the AI products of the future and intentionally, which is why it goes from Gen 9 to Gen 11. We've made substantial improvements that this node really brings relative to any prior NAND. A few of those are doubling the bit density versus Gen 9, but then also a 1.5X I/O speed target and focus on data transfer energy and really bringing that down relative to G9. So this G11 technology is the world's most advanced and it will ramp in the second-half of next year. Also it's based on wafer-to-wafer bonding technology which like I had described before we had mentioned we'll bring in wafer-to-wafer bonding technology at the right time when it's cost effective and it brings in capability that's important for the product specs at the time and this is the right timing for that technology. We'll be at more than 400 layers and we'll get more specifics on that next year closer to the launch dates. But as mentioned, it will be ramping in the second-half of 2027. And then beyond G11, we have a strong road map, not going to go into great detail on it today, but really focused on new materials, densifying the cell architecture and continuing to focus on that XYZ scaling going forward. So big generational leap with our Gen 11 NAND technology rolling out and excited to see how that really underpins the AI focus products we have going forward.
When we look at those products going forward, really 2 focus areas. Our Micron's focus is to ensure that we are capable of meeting customer needs on a variety of different higher performance NAND products. And there's really 2 focus areas here. One is on high IOPS AI class NAND, which is SLC based designs implemented in small blocks to design ultrafast memory storage products. And this is a key piece that meets several emerging use cases noted here and really is a major focus for Micron in terms of getting these products out the market over the next couple years. On the other side of this architecture and design path is high bandwidth AI class NAND focused on other emerging use cases and these ultimately are more costly and have to be implemented in partnership with customers in a way to ensure that they're meeting the mark and the cost point to drive the value proposition. But definitely enabling TSB stack NAND with logic based I/O to put closer to the accelerator. So not along the shoreline of the GPU as we don't think that has merit, but along closer positioning points to the compute itself to make use of this high performance NAND and the viability of that path. And then there's a number of looking at the segment view, a number of different segments that utilize a combination of those two architecture choices. As mentioned, if you go from data center to automotive, there's different cost sensitivity levels and different interactions with customers to determine which ones are appropriate and which ones we want to provide ultimately to customer demands.
Next, hitting on a couple of last topics. First on AI, accelerating AI. So how we use AI across Micron to enable innovation and execution and really position our team members with all the tools to deliver industry leading products going forward. And a couple of examples here just to highlight where we're at today. One on data center controller design and this is a demonstration that is confidently being executed right now delivering this controller in two times faster pace from silicon to tape out. So 50% less time from our prior generation of SSD controller to the new controller utilizing a variety of AI tools. Second example also confirmed now is developing an entire data center SSD product in this case a little bit faster than two X 60% less time and going from the prior generation to the next generation. I'm really leveraging AI generated firmware root cause analysis, enabling agents to do a significant amount of the core determination of product viability and then optimizing around the path to make that product work. So besides those two examples, definitely focus on basic physics all the way to smart manufacturing, which are impacting every single engineering employee at Micron and making them more successful. The next couple are around that I want to highlight today are around R&D investments really to enhance our future competitiveness and then a little bit about how we Co-innovate with customers.
So first on the long horizon R&D investments, we've announced several lately that are significant changes in how we've operated and how far we've looked out into the future, definitely ramping up our Micron Ventures efforts. And we've had some press on the increased capital commitment relative to Micron Ventures focusing on strengthen the ecosystem engagement. Albany Nanotech are announced focus on advanced lithography. They're really driving the high NA EUV road map for DRAM in particular at Albany with our team there focused on the next 5 to 10 years. And then the big announcement we did this summer on the 10 billion / 10 years focus on Micron Research Labs. Really with Micron taking a broader position in long term research outside of our current product road maps and under shaping what's next for the memory and compute systems of the future. And we look at an example of how we combine that for customer advantage. An example of customer collaboration really goes from a good example with Weka and Micron here as a company that we invested in as a from our venture fund and have built that into a partnership in supporting them and working out a business operate business arrangements with them to help them grow. So starting from an early investment to leading into business, so really interacting all the way from a start up like that to the focus with Meta, which is highlighted on this slide. Also relative to LPDDR6 and we put out a white paper that was released this morning, really a great partnership there in optimizing LPDDR6 for the data center and in partnering with them to understand how we take advantage of the unique server capabilities and higher reliability capabilities built into LPDDR6 and optimize that together. So really from start up through hyperscaler, engaging the customer interaction to improve Micron's future AI related products.
Overall, as a general point of view, really across our AI Co-invention opportunities, we're Co-imagining, Co-designing, Co-developing, Co-validating and then delivering at scale. And this opportunity is truly unique. It's very different than the way we interacted with customers even 3 or 4 years ago. But the opportunity to partner with customers to really understand from an early point of view what can be done with memory products, how customers can leverage that. And then ultimately building that into really having engineers working together on Co-designs and solving problems together all the way to the point of getting that final qualification with the customer Co-validating it and then ultimately ramping it and scale. OK. So all the emphasis today hopefully has given a little bit more perspective on how Micron's positioned. We feel this is the strongest position Micron's ever been in, in terms of technology and product leadership. Partnerships with customers have never been stronger. Our connections into the ecosystem are growing and we're going to continue to expand that really in a unique position and a very proud position, but absolutely one where we're focused on future execution in this growing complex era of complexity and making sure that we can leverage AI to deliver innovation and execution and even faster pace. So with that, I will conclude and I think we're ready for questions.
Operator
We will now begin the question and answer session. Please limit yourself to one question. If you would like to ask a question, please press *1 to raise your hand to withdraw your question. Press *1 again. If there are any follow up questions, please re raise your hand to re queue. We ask that you pick up your handset when asking a question to allow for optimum sound quality. If you are muted locally, Please remember to unmute your device. Please stand by while we compile the Q&A roster. Your first question comes from the line of Vivek Arya with Bank of America. Vivek, your line is now open.
Vivek Arya
Thanks for taking my question and thank you Scott for the very informative webinar. My question has to deal with how do you think the end customers are dealing with the fact that memory is becoming a bigger part right something half or more of the bill of materials. There is some talk of you know de stacking and making memory more workload specific. So the kind of the specific question to you is do you see DRAM content becoming more workload specific? You know, is it possible that when we look at inference workloads that the DRAM content might be lower or different than what it is in terms of training accelerators? Would that be a change from what was assumed before? So just how do you in your customer interaction see them dealing with this rising impact of memory and would there be a change in inference versus training DRAM content? Thank you.
Scott de Boer
Sure, thanks for the question. So I think that the starting piece to this answer and I'll go into a little more detail starting piece to this answer is for a given system memory content and memory bandwidth capability will make the system operate at a higher level as it increases. And that always there are ways to optimize for systems, but ultimately the system will work better with increasing memory content and increasing memory performance. So as we work with our individual customers to create the products that fit with their system design through time, they will of course make decisions relative to what the minimum system requirements are and they'll optimize relative to shipping their products and their business as well. But the underlying piece is their product will work better with the highest memory bandwidth and highest memory content. So eventually this will evolve through time. And as we've said, we're focused on both creating increasing our supply with all the investments that Nisha and we've talked about through earnings and other public times, but also through making sure our products can deliver higher and higher bandwidth through a number of these things like vertical HBM and vertical EIM so that the systems can be optimized and for sure if you look across the space of products, edge inference, mobile products, different kinds of small model products will have different memory optimizations. But in general, the underlying piece here is memory is still core to AI capability and AI system capability. And we'll continue to press to customers will continue to press to optimize that and inherently more memory does equal better system performance.
Operator
Your next question comes from the line of Timothy Arcury with UBS Securities. Timothy, your line is now open.
Timothy Arcury
Thanks a lot. Scott, you said that there's no viable scaling path for 4F^2. Can you just double click on that? Why would you know, we're hearing other competitors pushing this and why would they want to do that? And like why do you think that there's no scaling path forward is like an equipment readiness issue? And maybe do you think that there will be a time for 4F^2 and if so, when? Thanks.
Scott de Boer
Yeah. So I can't comment on why other customers or other suppliers would do things. I can only say from our investigation of this technology over the past couple decades. First off, it's a bit of a myth that 4F^2 actually provides anything versus 6F^2. It's the capacitor pitch that defines the DRAM. You can build the cells, the transistors underlying in different ways, but they still have to fit into the capacitor pitch, which sets the DRAM. So some of that is just kind of smoke and mirrors in terms of talking about 4F^2 versus 6F^2. Now when you look at a scaling path, you can go back a few nodes and absolutely 4F^2 can be built back a few nodes. No question about it. It's more complicated, it's more complex, it's more costly, but you can do that. When you look out from Micron's point of view as the leading edge technology company, when we look at scaling 4F^2 beyond where we're sitting today, there's, it's physics, there's fundamental problems with 4F^2 scaling that ultimately will lead to 3D DRAM coming in instead of 4F^2.
Operator
Your next question comes from the line of Ben Bajarin with Creative Strategies. Ben, your line is now open.
Ben Bajarin
Hi, thanks for taking my question. So Scott, just a quick one on how you think about memory road maps as it relates to next generation compute scaling for racks, meaning more the compute domain that everybody's talking about. So not just having one rack to run a model, but networking goes together to two or three or four and how that might impact memory when they can run larger models within compute racks networked as one compute domain.
Scott de Boer
So I think there's going to be a lot of different configurations of compute depending on the customers. And our focus is making sure we have the products that can optimize in any of those domains. As we've said, the next few years we don't see a period of time where memory is not going to be in short supply. And in the next two years as Sanjay said and we actually don't see a time when it comes into balance. So our focus whether it is in these different kinds of configurations or in the leading edge configurations of data centers today or even the edge in other devices that we create the types of memory products with the bits that we have that optimize the solution for those customers. So I think there are going to be different kinds of solutions there. They are all going to be memory intensive and whether our optimized LP solutions, LP6 solutions or DDR6 solutions are required in bigger volumes for some configurations or other configurations require high density or medium density products or more HBM I think we just are going to leverage our close collaboration and connections with customers to be sure we deliver. We have the products that they need for how they're going to build their racks.
Operator
Your next question comes from the line of Srini Pajuri with Royal Bank of Canada. Srini, your line is now open.
Srini Pajuri
Thank you. Thanks Scott for doing the presentation. My question is on the base die for HBM. You guys talked about moving to a foundry process node in the future. I'm just curious, you know, I know you didn't announce exactly what process node, but it does seem like it might need an advanced process node going forward and NVIDIA talked about potentially moving the memory controller into the base die. So if you could talk to us about, you know, what makes, you know, potentially at the advanced process node necessary for the base die. And then, you know, as you go vertical, you know, do you see anything changing as far as the base die is concerned? Or do you think that, you know, the advanced process is still kind of necessary? You know, depending on I don't know what kind of functionality I guess, you know, get into base die versus, you know, the GPU/XPU in the future. But when we go vertical, just trying to understand how, you know, you see the road map going forward.
Scott de Boer
Sure. So to start with the base die in the custom sense is absolutely a decision jointly with the customer that we build the custom product for. So in the example that you know, actually I won't use a specific customer for example, but if when we Co-design a base die and the certain logic elements that are desired to be put in that base die are generally an offload from GPU circuitry anyway onto the base die to put it closer to the memory. And so the best leverage is to utilize the advanced node that's appropriate for the customer. We have flexibility generally to a certain extent to optimize the memory IP around certainly around a more advanced node, but we would optimize it around the most cost effective node that meets the performance. And going forward as we said, we're on both our standard JEDEC design products and our custom products. We'll be using foundry node for both base, for both those base dies. And we haven't stated what nodes we're using, but we're using advanced nodes for both to enable capabilities. Really it's around power and capability into the base dies. So as we've talked about, and I think I talked about this time last year, for HBM4, optimal power and performance didn't require that. Some competitors used it, our HBM4 didn't. And it has power and performance strength as we said it would at that time. But for HBM4E, the performance, the speed and the power optimization does require more advanced CMOS. So when we look out to vertical HBM, it will again have functionality in the base that connects directly to the GPU and it'll provide. So it will still be as advanced nodes in the base on vertical HBM and it will have increasing functionality in that base die that can be leveraged there that connects directly to the GPU, again optimizing for quality, certainly quality and reliability of the VHBM product itself, but also optimizing for ultimate system performance power and leveraging advanced silicon to optimize the overall efficiency of what's on the accelerator chip below it. So moving what makes more sense onto the base die will still be a reality in vertical HBM time frame as well.
Operator
Your next question comes from the line of Daniel Newman with Futurum. Daniel, your line is now open.
Daniel Newman
Hey Scott, thanks for taking the time today. I thought, you know your slide where you showed sort of the AI increases on memory demand across training, inference and agentic and then physical really told a very interesting story about sort of how Micron needs to both align and be more strategic with its partners in order to scale, but in order to meet what we expect to see continued growth across all these areas across inference, agentic and physical AI. So what are some of the key areas of innovating, partnering and building processes, both serial parallel, they're going to enable you to keep up and deliver on sort of these insatiable demand that continues to grow.
Scott de Boer
Yeah, that's a good question. Thank you. And definitely one that we put a lot of focus into. So I think in the couple things that I would point out is one, although I only had one slide and a couple of examples on AI across our execution process, it is a major focus. Across the company and that improvement of 2X timeline, 2X shorter time to execution from innovation to high volume manufacturing. That is a key piece that we're well down the road on and is a major focus, but also a key piece that we are depending on to increase our bandwidth and being able to cover the kinds of solutions coming at us from the whole ecosystem. Second piece is very focused and targeted product development in alignment with customers and then in parallel on the technology front, enhancing our partnerships with key suppliers to make sure we're delivering specific capabilities. So whether it's across lithography areas or across packaging, hybrid bonding enablement or film processing, different things with key partners that we have need for enablement and we can see what to deliver certain aspects of the products our customers need. And we're strongly focused on deepening those partnerships. So all the way across our supply chain and then up to our customers making sure that we just focus very extensively on execution of this wide variety of things coming at us. And the bandwidth that we have across our engineering team increases substantially through the use of AI tools.
Operator
Your next question comes from the line of Atif Malik with Citi. Atif your line is now open.
Atif Malik
Thank you Scott and Satya for putting this together, especially the 3D DRAM versus 4F square road map update. My question is on the physical AI or near memory where Micron is also taking a different approach with edge inference memory EIM, which involves stacking low power LPDDR on top of the logic die versus peers process in memory, which embeds computing units inside the memory. Scott, can you talk about the merits of your approach versus peers?
Scott de Boer
Well, I can say that actually we have both product directions in flight, the performance of so and it's a bit of a balance. So when you look at processing in memory, there's certain capabilities that can be built in cost effectively into LPDDR and that balance and the system complexity of that is one set of considerations that we work with our customers on. But absolutely can say that we have processing and memory solutions in flight and in discussion with customers as well. The performance that we get from our vertical edge inference memory is just substantially higher. So it reaches a point where the customer needs more bandwidth than can be accomplished through standard PIM type capabilities and then a capacity that is also beneficial in these edge opportunities. So there are, you know it again is and we can also reach lower powers because of the use of a base die with LP and the logic and memory IP that can be built into that base die. We could have a substantially higher performing product for edge, vertical edge inference memory then we can with standard PIM inside of an LP. So it really is down to the customer interaction and customer collaboration to what type of solution benefits them most. And then we optimize the memory around that edge inference memory can provide a higher point of performance, which I think I had a few examples on the slide, but that can be tweaked with cost structure depending on how far the customer wants to go in terms of how much bandwidth and how much power. There's really a spectrum all the way from those numbers of sub pico Joule per bit kind of powers and those bandwidths that are good enough for edge devices. The spectrum really goes from there all the way up to HBM since the structure is similar. It's more about segmentation and design of the DRAMs than it is about the core technology. The core technology is largely common. It's more of a design element difference between that edge memory and the vertical HBM and we can optimize anywhere in between there depending on the customer needs. So it's really a platform that can be leveraged to meet different kinds of applications.
Operator
Our last question comes from the line of Mehdi Hosseini with Susquehanna International Group. AD. Your line is now open.
Mehdi Hosseini
Yes, thanks for taking my question. It's kind of when you go back to segmentation of HBM, you highlighted introduction of VHBM. And I want to double click on this. Can you help me understand how bandwidth is necessitating the VHBM? And how should we think about the trade off between bandwidth and density? I think there are some confusion and in my opinion bandwidth is priority number one and perhaps VHBM would give you that extra bandwidth and This is why is diversification. But I would like to hear how you see it especially as it relates to the underlying technology. Thank you.
Scott de Boer
Sure, Thanks Betty. So the key piece with VHBM is bandwidth as you point out, that is the enabler. If you think about the kind of bandwidth that can be accomplished and the power levels that can be accomplished by putting the structure directly on top of the next PU, that is the piece that can't really be done in a different way in terms of that much bandwidth gained. Now, capacity of course, is more complicated directly on top of GPU because it's a much more difficult thermal management challenge to go to multiple die stacks, although you have to go to higher capacities on vertical HBM as well. It doesn't start out as a product that can be built with a large number of die stacks and actually have the power and performance benefit and thermal management. So capacity scales at a different pace there and the system product ultimately for most systems or for many systems will be HBM5/5E in combination with vertical HBM to get the bandwidth and the system will be optimized around both those things. So capacity optimization is key and we're working hard to get the capacity up on vertical HBM. But these things, there's also the interplay of these things with trade ratio. So when you look at vertical HBM, it again has a very high trade ratio because of both because of the stacking, but also because of the optimization for bandwidth inherently makes the number of IOs much larger and which inherently reduces the die per wafer on the DRAM. So it's another balance point to all this. But the system vertical HBM ultimately is going to be a huge benefit to our customers as it comes in and provides primarily this bandwidth boost that you mentioned.
Operator
There are no further questions at this time. I will now turn the call back to Scott de Boer, President, Chief Technology and Products Officer for closing remarks.
Scott de Boer
OK, thank you for the opportunity to talk with you all today and good questions. Just wanted to re emphasize that we believe Micron is at its strongest position in history at this point in time. The technology underpinning our products is a key strength of Micron's and we're very focused on the execution it takes to continue that technology leadership. Our products built on that core technology are enabled in a very strong way with our customer collaboration. And we're set up to win in that space due to the depth of partnerships that we are building and have established. And ultimately in order to manage this complexity and the large number of customer demands, we are leading the way with AI implementation from basic physics through design and high volume manufacturing and really leveraging that AI to make sure that our execution is stronger than ever. So thank you very much for your time today. This concludes today's call. Thank you for attending. You may now disconnect.
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