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They’re all called '3D memory'—but what exactly are HBM, zHBM, and 400-layer NAND stacking? [AI Insights · Episode 2]
On August 5, $Samsung Electronics (005930.KR)$ At the FMS 2026 storage conference, concept models of zHBM and zNAND-O were showcased, along with the V10 BV-NAND featuring over 400 layers.
According to official Samsung Electronics documentation, the aforementioned products relate respectively tohigh-bandwidth memory, NAND flash, and three-dimensional integrationamong other distinct technological directions. Although their names all include"3D"or"stacking"concepts, their architectures, application scenarios, and commercialization stages differ significantly.
For investors focused on the AI supply chain, the key is not mastering specific fabrication processes, but rather understanding which problems these technologies address, whether they are currently in concept demonstration, customer validation, or mass production, and how they might eventually translate into corporate financial performance.
1. What roles do HBM and NAND each play?
An AI server can be understood as a systemthat must simultaneously handle computation, data retrieval, and long-term storage.。
AI acceleratorresponsible for executing computational tasks,。HBM and DRAMare responsible forquickly providing data currently in use,，NAND and SSDprimarily handlehigh-capacity data storage.。
HBM, or High Bandwidth Memory, is a type of DRAM. It stacks multiple layers of DRAM chips vertically and uses a wider data interface to increase the amount of data that can be transferred per unit of time.
NAND, on the other hand, emphasizes storage capacity and long-term data retention. Its data read speeds are typically lower than those of HBM, but it offers a lower cost per unit of capacity, making it suitable for storing model parameters, training data, and computation results.
In simple terms,HBM primarily addresses data transfer efficiency for AI chips, while NAND focuses on providing greater long-term data storage capacity.
II. Both involve 'stacking'—how do their structures differ?
The first typeYesVertical stacking inside HBM.
HBM stacks multiple layers of DRAM dies on top of each other and uses TSVs (Through-Silicon Vias) to connect different layers. TSVs can be thought of as vertical data channels passing through multiple chip layers, enabling more direct data transfer between memory layers.
Current HBM products from Samsung and SK Hynix both follow this fundamental approach of multi-layer DRAM stacking. For example, Samsung’s HBM3E offers a 12-layer version, and SK Hynix similarly increases DRAM stack height to boost capacity and data transfer performance.
The second typeYesAI accelerators placed side by side with HBM.
Today’s mainstream AI chips typically integrate GPUs or other AI accelerators alongside multiple HBM stacks within the same package, though the processor and HBM remain positioned next to each other. This architecture is commonly referred to as 2.5D packaging. In simple terms,AI accelerators and HBM are already housed within the same package, but data is still primarily transmitted via horizontal interconnects.
The third approach isSamsung’s newly showcased zHBM
Compared with the current mainstream approach—where processors and HBM are placed side by side—zHBM attempts a more advanced vertical integration architecture, positioning memory directly above the AI accelerator.
In simple terms,this shifts the layout from 'side-by-side' to 'stacked vertically,' further shortening data transmission distances and enabling greater memory capacity within the same package footprint.
Samsung stated that its next-generation interface system using zHBM targets approximately eight times the performance of HBM5; leveraging next-generation wafer bonding technology, it aims for over ten times the memory density of HBM5, triple the energy efficiency, and more than a 50% reduction in thermal resistance.
III. Why are bandwidth, capacity, energy efficiency, and thermal management important?
· Bandwidth reflects how much data a channel can transfer per unit of time.The faster an AI chip computes, the more data it typically needs to fetch per unit time. If memory cannot supply data quickly enough, some compute units must wait—meaning even a GPU with high computational capability may not perform to its full potential. The industry commonly refers to this bottleneck, where compute performance is constrained by memory bandwidth, as thememory wallorMemory Bottleneck”。
· Capacity determines how many model parameters and working data can be stored near the AI accelerator.
· DensityThe emphasis is on how much memory can be integrated within a limited package footprint or physical space. For AI servers, package area, rack space, and interconnect distances are all constrained resources.
· Energy efficiencyThis reflects the amount of power consumed to complete the same task. AI data centers incur not only chip procurement costs but also expenses related to power supply, cooling, and daily operations.
· heat dissipationThermal management is a critical challenge that must be addressed in 3D stacking. Shorter distances between chips reduce data transmission paths, but denser structures can lead to more concentrated heat. Therefore, 3D integration must simultaneously address interconnect efficiency and thermal management.
Samsung has identified reducing thermal resistance as one of the primary design goals for its zHBM. SK hynix has also enhanced the thermal management capabilities of its HBM products through advanced packaging materials and thermal design. Based on the publicly disclosed technical roadmaps from Samsung and SK hynix,the competitive metrics for memory products are expanding beyond bandwidth and capacity to include power consumption, thermal performance, and system stability.
It takes time for a technology to move from a product launch announcement to appearing in financial statements—it must go through engineering development, customer validation, mass production, and actual shipments. Therefore, after understanding performance specifications, one must also assesswhich commercialization stage the relevant products are currently at。
Fourth, after grasping the technology, one must also evaluate how far along it is in the commercialization process
Semiconductor companies frequently useterms such as 'demonstration,' 'sample shipment,' 'customer validation,' and 'volume production and shipment.'Although all these terms indicate product progress, they correspond to different commercialization stages.
Conceptual modelsare primarily used to showcase future product architectures and technological directions.
Samsung's recently exhibited zHBM and zNAND-O are conceptual models. These products illustrate potential structures for next-generation memory but do not indicate confirmed volume production timelines or equate directly to secured customer orders.
Sample shipment to customerssignifies that the product has entered the customer testing phase.
After memory manufacturers deliver product samples to customers, the customers must validate performance metrics such as speed, power consumption, stability, packaging, and thermal characteristics to confirm compatibility with their AI accelerators. For instance, Samsung’s prior delivery of HBM4E samples to key customers indicates the product has transitioned from internal development to customer testing, though large-scale procurement still depends on validation outcomes.
Volume production and shipmentindicates that the product has entered actual sales.
According to publicly available information from Samsung,its HBM4 has already entered mass production and commercial shipments. In its second-quarter earnings announcement, SK hynix stated thatHBM4 is already in mass production and shipping, and it is enhancing visibility into future orders through multi-year supply agreements.
Therefore, even when both are technology-related news, their implications for corporate operations differ.
Conceptual models primarily reflect future technological directions.
Customer sampling indicates that the product is beginning to compete for procurement qualification.
Mass production and shipment are much closer to generating revenue and profit contributions.
A technology launch addresses whether a product can be realized; customer validation determines whether it can enter the procurement system; and mass production with shipment affects whether the product can generate actual revenue.
After clarifying the technological approaches and commercialization stages, let’s return to another key highlight of Samsung’s recent announcement: the V10 BV-NAND with over 400 layers. It is also referred to as 3D storage, but its stacking method differs from that used in zHBM.
5. Why are both 400-layer NAND and zHBM called 3D storage?
Samsung has announced its V10 BV-NAND with more than 400 layers. Here, '400 layers' does not mean stacking 400 complete SSDs together, but rather vertically arrangingmemory cells within the NAND chip.
Traditional planar NAND is akin to continuously building single-story houses on a plot of land; 3D NAND, by contrast, constructs high-rise buildings—adding layers vertically to store more data within the same footprint.
Samsung’s newly showcased V10 BV-NAND employs a bonded architecture. The company states that its storage density has increased by approximately 58% compared to the previous generation.
SK Hynix is also advancing new NAND products tailored for AI inference scenarios. The company, along with its partners, positions HBF as a new memory tier between HBM and SSDs, aiming to strike a balance among capacity, speed, and energy efficiency.
These technologies collectively address the same industry challenge:As AI chip computing speeds increase, can data be delivered to the chip in time, and can it be stored at a reasonable cost?
Samsung's demonstration of zHBM this time provides a technical case study of how AI memory is evolving from side-by-side placement toward higher levels of vertical integration. Meanwhile, according to SK Hynix’s public disclosures, the company is advancing both the mass production of HBM4 and multi-year supply agreements on one front, while jointly promoting HBF standardization with SanDisk on another—addressing, respectively, the commercialization of existing high-bandwidth memory and the exploration of new memory tiers for AI inference scenarios.
For investors tracking the relevant industrial chain, a more informative observation sequence is:First assess the problem the technology aims to solve, then determine the product’s current development stage, and finally monitor customer validation, mass production progress, actual shipments, and financial contribution.
Sources: Samsung Global Newsroom, 'Samsung Unveils Next-Gen 3D-Memory Vision at FMS 2026,' August 5, 2026; Samsung Semiconductor HBM and V-NAND technical materials; SK Hynix Q2 2026 earnings announcement, July 29, 2026; SK Hynix public materials on HBF and AI storage products, February–August 2026.
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