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Sector Deep Dive | Glass Substrates Part I: Ushering in a New Era of Advanced Packaging

💡 Key Insight

– Glass substrates, with their low coefficient of thermal expansion, extremely low dielectric loss, ultra-high flatness, and exceptional dimensional stability, are replacing traditional organic substrates (BT/ABF) to become the leading material choice for the 'next-generation base' in 2.5D/3D advanced packaging.

– $Taiwan Semiconductor (TSM.US)$CoPoS (panel-based glass substrate approach) and $Intel (INTC.US)$ EMIB + glass core substrates (integrated approach) are advancing in parallel, with mass production timelines becoming increasingly clear for 2027–2028.

– $Corning (GLW.US)$ is the most leveraged beneficiary across the supply chain: dual growth drivers from optical communications and packaging glass, benefiting regardless of Taiwan Semiconductor or Intel technology routes.

Growth Thesis：Continuously rising AI compute density → Ultra-large chip packaging areas exceed the boundary of 12-inch circular wafers → Square glass panels have become the only physically viable path to mass production. Taiwan Semiconductor’s panel utilization target (90%+) and NVIDIA’s demand for ultra-large chips are jointly accelerating the transition of glass substrates from validation to mass production.

Positioning recommendation:Prioritize early positioning in upstream material leaders$Corning (GLW.US)$ (Dual-core drivers in sync, technology-path neutral, highest elasticity); $Taiwan Semiconductor (TSM.US)$ Benefits from extended valuation duration rather than short-term revenue surge; $Intel (INTC.US)$ An optionality-driven play—successful mass production would yield greater upside elasticity than Taiwan Semiconductor; monitor with light positioning.

Risk Warning:TGV process yield is the core bottleneck for mass production, with a risk of timeline delays; silicon interposers still hold an advantage in high-bandwidth scenarios such as HBM-GPU direct connectivity in the near term; Corning’s valuation, after recent gains, appears stretched and faces downside pressure ahead of its Q2 earnings report.

I. Packaging Architecture Evolution: The Rationale for Glass Material Adoption

First,梳理 the evolution of chip packaging architectures to clarify the specific applications of glass materials.

– 2D Packaging (Traditional Packaging)：

◦ All chip dies are individually packagedand arranged side by sideon an organic substrate. Chips are only arranged horizontally (along the X/Y axes) relative to each other.

◦ Chips cannot communicate directly with each other. Signals must travel through the carrier substrate.

◦ Lowest cost, but with wide trace spacing, high signal latency, and extremely low bandwidth

◦ Unable to meet the demands of modern high-compute chips

– 2.5D Packaging (Represented by Taiwan Semiconductor's CoWoS)：

◦ The side-by-side relationship between the Logic Chip on the right and the Logic Base on the left in Table 1. Spatially, the chips remain horizontally (X/Y axis) aligned.

◦ An interposer (the yellow part in the diagram) is inserted between the chip and the underlying substrate. The surface of the interposer uses semiconductor photolithography to etch an extremely dense and fine redistribution layer (RDL) for inter-chip communication, eliminating the need to route signals through the underlying carrier substrate (the purple part in the diagram) and back up again.The RDL provides shorter paths and lower signal loss.The lines connecting the PHY physical interfaces in the middle of the interposer constitute the redistribution layer (RDL). An RDL is inserted between the chip and the interposer.

◦ Silicon is currently the dominant material used for interposers,with glass interposers emerging as one potential alternative.

– 3D Packaging (Represented by HBM)：

◦ Chips are stacked vertically; for example, the HBM shown in the upper-left corner of Figure 1 consists of multiple DRAM layers vertically stacked. Current mainstream HBM configurations feature 8 or 12 layers.

◦ Data can travel directly through the vertical stack, reducing physical distances to the micrometer scale. In 3D stacking, chips are directly interconnected internally via through-silicon vias (TSVs) and microbumps.

◦ This approach delivers extremely high bandwidth and ultra-low latency, but poses significant challenges in thermal management, process complexity, and yield requirements.

Figure 1: Schematic illustration of high-density interconnect packaging for HBM and logic chips

Source: SK hynix, compiled by Futu Securities

II. Applications of Glass Substrates

The primary applications of glass substrates fall into two categories: glass interposers and glass core substrates.

– Glass Interposer: Offers lower electrical loss,eliminates the need for insulation processes, and is also more cost-effective. However, silicon interposers are manufactured using semiconductor photolithography techniques, enabling pitches below 1 micron. In contrast, due to limitations in TGV (Through-Glass Via) technology, glass substrates currently achieve a minimum pitch of only 2 microns, and microcracks easily form along TGV sidewalls under thermal cycling conditions. For the highest-bandwidth connections—such as those between HBM and GPUs—silicon still holds an advantage.

– Glass Core Substrate: Glass replaces organic core materials like BT in traditional IC packages and enables fine-pitch routing and signal routing through ABF buildup layers. The area near the purple region shown below illustrates this concept—glass replaces the central portion. The shift to glass is driven by the fact that traditional organic substrates are approaching material limits in large-format, high-density interconnect scenarios, where dimensional stability and high-speed signal transmission have become critical constraints. Glass offers low dielectric loss, high surface flatness, and excellent dimensional stability. Additionally, panels or trays used for large-format packaging are transitioning from circular to square shapes because chips themselves are square,and square panels offer higher area utilization.Silicon, due to its material properties and processing characteristics, cannot easily adapt to large-format square panels like glass can; thus, this trend supports a certain degree of process continuity in shifting substrates toward glass.

Figure 2: Schematic illustration of FC-BGA substrate structure

Source:TOPPAN,Compiled by Futu Securities

III. Glass substrate applications are dominated by two major manufacturers

🔍 Taiwan Semiconductor: CoPoS as the next-generation advanced packaging technology following CoWoS

$Taiwan Semiconductor (TSM.US)$ is advancing its glass substrate roadmap in two phases:

· Phase One — CoPoS (planned for mass production in H2 2028)

– Usessquare glass panelsto replace circular wafers as production carriers, increasing panel utilization from <80% to over 90%

– Replaces silicon/resin interposers with specialty electronic-grade glass, while retaining silicon bridges for connections between GPUs and HBM

– This year is a critical validation period for equipment and materials suppliers, with trial production expected to begin in 2027.

· Phase Two (around 2030): Organic substrates will be further replaced by glass-core substrates.

· Significance of glass substrates for Taiwan Semiconductor:Glass substrates are not a near-term catalyst for revenue surges for Taiwan Semiconductor, but rather a support for valuation duration.

They address bottlenecks such as cost and warpage in large-area CoWoS packaging, thereby solidifying its existing dominance in advanced packaging.

Looking solely at changes in revenue composition: advanced packaging revenue share is projected to rise from approximately 13% in 2026E to around 16.7% in 2027E (an increase of about 3.7 percentage points). This growth is not entirely attributable to glass substrates. However, the advancement of glass substrates and CoPoS helps reinforce market confidence that this trend will remain sustainable through 2028–2030.

· Impact on valuation:For valuation purposes, the significance of glass substrates lies in raising the ceiling and extending duration.。The true valuation logic lies in alleviating market concerns over the physical limitations of CoWoS., maintaining market confidence that ultra-large system-in-package solutions can still be supported beyond 2028.elevating Taiwan Semiconductor from a 'wafer foundry + packaging house' to a full system integration platform

💡Overall assessment: In the short term, the use of glass-based materials offers limited upside to Taiwan Semiconductor's overall valuation. Its primary role is helping Taiwan Semiconductor maintain a relatively high valuation level.

Figure 3: Taiwan Semiconductor’s advanced packaging roadmap

Source:TSMC,Compiled by Futu Securities

🔍 Intel: A bold, all-in-one play with option-like characteristics

$Intel (INTC.US)$ is the world’s earliest and most aggressive proponent of glass substrates (publicly unveiling its approach first in 2023). Intel has long pursued apackaging roadmap centered on EMIB, designed to compete against Taiwan Semiconductor’s CoWoS. EMIB employsEmbedded silicon bridge solution, which embeds only small silicon bridges in critical chiplet interconnect regions as an alternative to a full silicon interposer. Intel'sglass roadmapinvolves using large-format square glass panels for carriers and directly replacing the substrate layer with specialty glass. In an optimistic scenario, volume production will begin in 2027,with baseline expectations pointing to volume production in 2028。

- The core difference between the two roadmaps lies in their strategic positioning of glass applications

· Intel is the 'disruptor': Lagging behind Taiwan Semiconductor in overall foundry process technology and customer ecosystem, Intel needs to overcome the high technical barrier of glass-core substrates to achieve physical stability for ultra-large packages measuring 80–100mm—glass is Intel’s key differentiator to break away from Taiwan Semiconductor。

· Taiwan Semiconductor already holds major client orders, and its CoWoS capacity is oversubscribed. Its most urgent task is improving panel utilization—for example, NVIDIA’s next-generation ultra-large chip is so big that cutting it from traditional 12-inch round wafers results in significant edge waste. Therefore, Taiwan Semiconductor’s immediate priority is adopting large square panels to boost utilization above 90%, rather than hastily replacing organic substrates with relatively fragile glass.—Thus, Taiwan Semiconductor has opted for aphased approach, Intel choseall in one step。

💡Overall assessment: Intel holds a strong industrial position in glass substrates, but for Intel, glass substrates represent more of an optionality value within advanced packaging. Going forward, the potential uplift to its valuation is greater than that for Taiwan Semiconductor. However, even with growth in advanced packaging revenue, it remains insufficient in the near term to materially reshape the company’s overall income statement.

🔍 Corning: A more elastic beneficiary within the glass substrate supply chain

$Corning (GLW.US)$ Corning is a global leader in materials, with its two largest business segments by revenue as follows: first, optical communications, accounting for approximately 40% of revenue; second, glass, contributing roughly 30%.

· Revenue breakdown:

– Optical Communications(~40% of revenue): Fiber optic demand from AI compute clusters surged in Q1–Q2 this year, and fiber prices are clearly on an upward trend for the full year, providing notable stock price catalysts in April–May.

– Glass business(~30% of revenue): Currently dominated by consumer electronics and displays, but the advanced packaging segment within glass exhibits significantly higher elasticity, and its share of the glass business is rising.

· Premiumization logic for packaging glass:

·Sold to panel manufacturers: priced per square meter, leading to price competition.

·Sold to Taiwan Semiconductor or Intel: technology premium priced per 'chip' or 'wafer.' Once scaled up, semiconductor glass will significantly boost the profit margins of the entire glass segment.

Regardless of whether Taiwan Semiconductor or Intel achieves mass production first, the rigid demand for upstream glass materials is certain. All upstream electronic-grade glass is supplied by Corning, making it a monopolistic upstream node in a 'winner-takes-all' supply chain.

· New Growth Curve — GlassBridge

More importantly, Corning’s optical communications and glass materials businesses exhibit strong overall operational synergy.

On June 24, Corning announced GlassBridge glass-based optical interconnect technology. This technology is fundamentally a connector platform that interfaces optical fibers directly with photonic integrated circuits (PICs), enabling direct fiber coupling into photonic chips. This positions Corning deeply within the passive photonic components essential to CPO and NPO architectures and provides a partial alternative to the FAU (Fiber Array Unit) products offered by TFC (Tianfu Communications).

· The CPO Era: Glass Evolves from Substrate to Shared Platform

In the CPO era, glass is no longer just a substrate—it becomes a shared platform for both electrical and optical interconnects.

However, note that GlassBridge still needs to undergo qualification certification, reliability testing, and yield ramp-up before large-scale deployment. It will not disrupt existing CPO generational solutions within the next 1–2 years, though this does not diminish its long-term investment value.

Following its recent rally, Corning's valuation has become relatively full, and the stock price may face downward pressure ahead of its second-quarter earnings report.Entering on a pullback is preferable to chasing the price higher.。

💡 Overall assessment: Corning is gradually transitioning from a cyclical materials stock into an AI interconnect-layer asset. However, after its recent rally, Corning’s valuation has already become relatively full, and investors should wait for a pullback to find a better entry point. The share price may face downward pressure ahead of the Q2 earnings report.

Figure 4: Corning’s annualized sales run rate outperforms its Springboard program targets

Source: Corning, compiled by Futu Securities

IV. Risk Warnings

– Technology development falls short of expectations

– Market demand falls short of expectations

[Investment Advisory Information]

Tim Yang | SFC Central Reference Number: BUR210

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