Huawei's 'Tau Law': A Comprehensive Overview of Core Companies

On May 25, 2026, He Tingbo, Huawei Board Member and President of the Semiconductor Business Unit, formally introduced Tao’s Law (τ Law) at ISCAS 2026. This marks the first time China has proposed a new principle guiding global semiconductor industry development.

1. τ (tau, pronounced 'Tao') represents the time constant in circuit theory—the time required for a signal to transition from one state to another. The smaller the τ, the faster the circuit switching speed.

Traditional Moore’s Law focuses on continuously shrinking transistor dimensions (geometric scaling).

Tao’s Law shifts toward temporal scaling: persistently reducing signal propagation delay without relying on extreme linewidth miniaturization.

2. Core Implementation Approach—Logic Folding

Conventional chip circuit layouts are two-dimensional planes, requiring signals to travel long horizontal distances. Logic folding expands the layout from a single layer to multiple stacked layers, vertically folding critical paths and replacing long planar interconnects with short vertical ones, thereby significantly reducing the time constant τ.

3. Achievements to Date and Future Targets

Over the past six years, Huawei has designed and mass-produced 381 chips adhering to Tao's Law.

Plans are in place to launch a Kirin chip featuring logical folding technology in the fall of 2026.

By 2031, high-end chips based on Tao's Law are expected to achieve performance equivalent to that of a 1.4-nanometer process node.

This article compiles a list of companies associated with Huawei’s Tao’s Law below. We encourage readers to like and bookmark this post for future reference. The content provided is for informational and logical interpretation purposes only and does not constitute investment advice. Follow me for daily breakdowns of core market themes and their underlying logic.

Tao’s Law requires optimizing transistor and interconnect layouts at the circuit level to reduce the time constant τ. EDA tools are integral throughout the entire chip design, simulation, and verification workflow. Behind Huawei’s 381 mass-produced chips lies a mature, fully localized EDA toolchain. The following companies hold key positions in the EDA field:

Empyrean holds the largest market share among A-share-listed EDA vendors, with approximately 6% of the domestic market. It is currently China’s largest and most comprehensive EDA company. Empyrean offers a full suite of EDA tools for analog circuit design, as well as digital design EDA solutions, providing foundational support for the circuit-level optimizations required by Tao’s Law.

Primarius ranks second among A-share EDA vendors by market share, with core strengths in device modeling and verification EDA tools. The company has built a complete toolchain covering device modeling, circuit simulation, and yield analysis. Given Tao’s Law’s stringent requirements for precise optimization of resistance and capacitance in transistor interconnects, Primarius’ capabilities in physical device modeling can be directly integrated into Huawei’s chip design flow.

It ranks third among A-share companies in EDA tool market share, focusing on manufacturing-oriented EDA tools—particularly those enhancing chip yield and test chip design. The company's yield enhancement solutions serve as a critical bridge between wafer foundries and design firms. As logic folding technology moves into mass production, the yield ramp-up process will heavily rely on yield management EDA tools like those offered by Guangli Micro.

Through its subsidiary Jianyuan Fund, it indirectly holds approximately 7.58% of Huada Jiutian. While Shentong Metro itself is not a pure-play EDA company, as a significant shareholder of Huada Jiutian, it stands to benefit from valuation uplift in domestic EDA firms driven by Tao’s Law.

It has independently developed TangDynasty, a full-flow FPGA-specific EDA software suite. FPGA EDA tools are extremely complex, and Anlogic is one of the few domestic companies capable of providing end-to-end solutions—from logic synthesis to place-and-route. Tao’s Law emphasizes architectural innovation, and FPGAs are indispensable for verification and prototyping; thus, Anlogic’s EDA tools will indirectly benefit from Huawei’s ecosystem demand for domestically produced FPGAs and their accompanying toolchains.

It has invested in and holds a 4.67% stake in Qingdao Zhancheng Technology, which specializes in IC design EDA tools focused on physical verification and layout-related domains. Si-Ware Electronics itself is a MEMS foundry, and through this strategic investment, it has established a dual synergy between manufacturing and EDA tools.

It possesses fully proprietary FPGA-supporting EDA tools covering the entire design flow, enabling support for its self-developed FPGA products. The company holds a leading position in China’s high-reliability FPGA segment, and its EDA tools have undergone extensive internal validation. Logic folding designs promoted by Tao’s Law may be first implemented in FPGA chips, and Fudan Microelectronics’ integrated hardware-software capabilities will benefit accordingly.

As the primary developer of Zhangjiang Science City, the company has invested in the Shanghai EDA Innovation Center and is committed to building a full-stack domestic EDA ecosystem. Its business model centers more on acting as an industrial platform and making ecosystem-driven investments rather than directly developing EDA tools, though it benefits from the regional clustering advantages of the industry.

The company independently develops and procures EDA software for designing high-power semiconductor products. While its core business focuses on power semiconductors—distinct from the advanced logic chip EDA market—the design philosophy championed by 'Tao's Law,' which emphasizes architecture over process nodes, could also extend into the power device segment. TBEA Semiconductor’s in-house EDA capabilities thus represent a key differentiator.

The company has built its own integrated circuit EDA design platform, primarily used for the independent development of aerospace-grade chips. With deep expertise in high-reliability and radiation-hardened chips, its self-developed EDA platform reflects a strong demand for design tool autonomy and aligns closely with the innovation-driven rationale underlying 'Tao's Law.'

The company holds a stake in Zhongke Yihaiwei, whose team has independently developed EDA tools supporting its FPGA products. Through this equity investment, Eastone Technology indirectly possesses FPGA-related EDA capabilities, giving it thematic exposure amid the ongoing wave of domestic substitution.

Its subsidiary, Shenzhen Capital Group (Shenzhen Innovation Investment Group), previously invested in Huada Jiutian. Guangdong Electric Power Group A holds an extremely indirect stake in Huada Jiutian through multiple layers of ownership, resulting in a relatively long equity chain and limited upside elasticity.

Logic folding upgrades circuit layouts from single-layer planar structures to multi-layer stacked architectures, essentially using 3D packaging to achieve short-distance vertical interconnects. This creates a firm demand for advanced packaging technologies: multi-die stacking, through-silicon vias (TSVs), hybrid bonding, and related processes have become essential. The following companies are core domestic participants in advanced packaging and chiplet technologies:

Ranked first in China for progress in advanced packaging technology, Tongfu Microelectronics has already mass-produced chiplet-based CPU/GPU products for AMD. The company possesses a complete 2.5D/3D packaging platform, including TSV, Fan-out, and Hybrid Bonding processes. AMD is the most successful commercial benchmark for chiplets, and as its core OSAT partner, Tongfu has fully validated the entire workflow—from technology development to high-volume manufacturing—making it the most likely candidate to handle Huawei’s logic-folding chip packaging requirements.

Ranked second in China for progress in advanced packaging technology, JCET has already mass-produced various advanced packaging products (such as SiP, Fan-out, and WLCSP). As the world’s third-largest OSAT provider, JCET benefits from significant scale advantages. Although its current chiplet-related volume orders lag behind Tongfu Microelectronics, its vast production capacity and broad customer base position it well to rapidly catch up.

Ranked third in China for progress in advanced packaging technology, Hua Tian Technology has achieved mass production of advanced packaging products. The company focuses on high-density packaging and has established capabilities in FC, TSV, and SiP technologies. Its strengths lie in cost control and rapid customer responsiveness, positioning it to capture a share of packaging and testing orders once logic folding technology matures.

Advanced packaging accounts for nearly 100% of its revenue, making NSI a pure-play advanced packaging company. It specializes in high-end OSAT services, with products including QFN, BGA, and SiP. Due to its relatively small scale and high business focus, NSI typically exhibits greater earnings sensitivity within Moore's Law–related investment themes.

Its cloud AI chip, the Siyuan 370, has already adopted Chiplet technology, representing a typical commercial implementation of Chiplet architecture in China. Cambricon itself is an AI chip design company and does not directly engage in packaging, but its successful adoption of Chiplet demonstrates the feasibility of this technological approach. Moore's Second Law will further accelerate the adoption of Chiplet technology in AI chips, and as an early mover, Cambricon is well-positioned to gain a first-mover advantage in design methodologies.

It offers a high-end application processor platform based on Chiplet architecture. VeriSilicon is a chip design services company (providing IP and design platforms) with an extensive Chiplet IP portfolio and strong system integration capabilities. The multi-die stacking designs driven by Moore's Second Law will increase demand for Chiplet design methodologies, interface IPs, and on-chip networks (NoCs), and VeriSilicon’s platform capabilities are expected to translate into higher licensing revenue.

Its products cover packaging types such as DFN, PDFN, and QFN, among which QFN is a foundational package type in advanced packaging and testing. The company’s technology level places it within China’s mainstream tier and it stands to benefit from the overall recovery in semiconductor packaging and testing and the domestic substitution trend.

It primarily manufactures back-end advanced packaging equipment for semiconductors, such as die bonders and sorters. Equipment suppliers are among the first to benefit during periods of capacity expansion in advanced packaging.

The company’s subsidiary, Suzhou Keda Optoelectronics, has accumulated expertise in advanced packaging technologies, primarily focusing on wafer-level packaging and TSV (through-silicon via). It is currently still in the phase of technological accumulation and market expansion.

The company has entered the advanced packaging sector through equity investments and subsidiaries, with its technology currently in the accumulation phase. Its core business is semiconductor discrete devices.

The company is involved in semiconductor packaging molds and equipment, and its advanced packaging capabilities are currently in a technology accumulation phase.

Compressing the time constant τ depends not only on circuit design but also requires optimization at the device level—such as transistor structure, interconnect materials, and process parameters. These optimizations must ultimately be implemented within the foundry’s process platforms and design rules. Additionally, Huawei’s logic-folded Kirin chip, scheduled for launch in the fall of 2026, will require a foundry to complete tape-out and mass production. All major domestic foundries stand a chance to secure this historic order:

SMIC is the undisputed leader in wafer foundry services in mainland China, ranking fourth globally and first domestically. The company possesses mature 14nm and enhanced processes and has FinFET advanced node capabilities. The logic-folding technology advocated by Tao’s Law fundamentally relies on design-technology co-optimization (DTCO). As the most technologically advanced foundry in China, SMIC is the most likely candidate to become the primary supplier for Huawei’s next-generation Kirin chips. The company also benefits from the broader trend of capacity shifting toward domestically produced chips across the entire semiconductor supply chain.

Ranked sixth globally and second in China in wafer foundry services, Hua Hong specializes in power devices, analog chips, and embedded non-volatile memory. Although its advanced process capabilities lag behind SMIC’s, Hua Hong has deep expertise in specialty process technologies. Tao’s Law-based 'logic folding' does not necessarily require cutting-edge nodes like 5nm or 3nm; by combining mature process nodes with innovative 3D stacking designs, Hua Hong could potentially fulfill some of Huawei’s foundry requirements for edge computing or IoT chips.

Ranked ninth globally and third nationally in wafer foundry, JHICC primarily focuses on display driver ICs (DDICs), MCUs, and other products. The company’s technology nodes are mainly based on mature processes ranging from 40nm to 90nm. Although it lags behind leading-edge logic chip foundries, JHICC is positioned to capture more domestic design companies’ orders shifting to mature-node foundry capacity amid the nationwide push for full supply-chain localization driven by Tao’s Law.

Specializing in discrete devices, analog ICs, and specialty IC foundry services, YD Microelectronics generates annual revenue of approximately RMB 2.056 billion. Its products primarily serve high-reliability and industrial control applications. The ripple effects of Tao’s Law may extend to design methodologies for analog and mixed-signal chips, and as a specialty IC foundry, YD Microelectronics stands to benefit from the broader trend of domestic substitution.

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Disclaimer: All content provided herein is for informational and analytical purposes only, intended solely for learning and discussion. It does not constitute any form of investment advice. The publication of this article has no correlation whatsoever with the stock performance of any mentioned companies. Do not use this content as a basis for investment decisions. You are solely responsible for your own investment choices. The market involves risks; please invest prudently.

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