With the support of the Questa and Veloce platforms, Siemens EDA achieves comprehensive acceleration in functional verification

The following article originates from Siemens EDA, authored by SIEMENS.

As semiconductor process technology continues to evolve and system complexity keeps rising, the integration scale of a single chip has rapidly increased from hundreds of millions of gates to tens of billions of gates. At the same time, market windows are continuously shrinking, and product launch cycles are getting shorter instead of longer: In the consumer electronics sector, flagship smart devices require major updates almost every year; even in highly safety and reliability-demanding fields such as autonomous driving and smart cockpit systems in the automotive industry, there is fierce competition with rapid iteration and multiple solutions being developed simultaneously.

The Questa™ One Intelligent Verification Platform and Veloce™ CS Hardware Emulation Platform from Siemens EDA are comprehensively accelerating the chip functional verification process through the intelligent evolution of verification tools and the deep application of system-level, software-hardware co-verification, profoundly reshaping the overall paradigm and efficiency boundaries of chip design.

01 This OneAI-driven technology brings a faster verification engine

The EDA verification field faces core challenges such as long verification cycles and heavy workloads due to increasing design complexity. Customers urgently hope to accelerate verification convergence and uncover deeper issues through exhaustive analysis. Meanwhile, the intelligence of EDA tools has become crucial for improving design quality and reducing error rates. As AI technology gradually matures in the EDA field, it brings revolutionary changes to chip design, significantly enhancing efficiency and quality while lowering development costs and shortening time-to-market.

The Questa One intelligent verification software platform introduced by Siemens EDA leverages AI technology to enhance connectivity, data-driven approaches, and scalability, breaking through limitations in IC verification processes. It helps engineering teams effectively boost productivity and supports large-scale complex designs ranging from IP to system-on-chip (SoC) and even larger systems.

Questa One redefines IC verification from a reactive process into a self-optimizing intelligent system. By integrating AI-driven automation, predictive analytics, and seamless workflow connections, it provides faster functionality, fault simulation, and formal verification engines. Simulation time can be reduced to one-sixth of the original duration, and manual testing volume can be cut by 10 to 100 times, significantly shortening the verification cycle and reducing manual workload.

Particularly noteworthy is its breakthrough in DFT verification. With semiconductor technology nodes continuously shrinking, device defect density rises, and process variability intensifies, making traditional test methods inadequate for detecting new subtle defects and aging effects. Additionally, chips now integrate billions of transistors and heterogeneous IP cores, causing test data volumes to surge and power constraints to tighten, further driving up the cost and complexity of DFT implementation. Moreover, to meet the full lifecycle reliability requirements of high-end applications like automotive and aerospace, DFT technology must cover end-to-end assurance from manufacturing to decommissioning.

To address these challenges, the Questa One DFT verification solution offers significant efficiency advantages through its comprehensive features and seamless integration with Tessent solutions, enabling design teams to efficiently complete DFT sign-off:

Static analysis capabilities:

Supports equivalence verification from pre-synthesis RTL to post-synthesis.

Automation commands:

Seamless clock domain/reset domain (CDC/RDC) analysis post-MBIST insertion;

Glitch SVA generation:

Automated protocol SVA generation for glitch scenario analysis;

Enhanced gate-level simulation performance:

Significant improvement in simulation efficiency;

Scalable functional fault grading:

Improved verification quality through enhanced structural scan defect coverage;

DFT-aware debugging and X-propagation analysis:

Accurate identification of DFT-related design issues;

Software-aware verification IP:

Accelerate the built-in self-test (IST) verification process.

The Questa One Sim DX DFT simulation acceleration solution works in tandem with the Tessent semiconductor lifecycle solution, providing an end-to-end solution that delivers the efficiency and performance advantages required for ATPG and MBIST pattern validation. This joint solution significantly reduces the risk of DFT sign-off becoming a bottleneck in the tape-out process. Its benefits are far-reaching, enhancing efficiency and performance during compilation, optimization, and simulation stages.

Yang Geng, Head of the Digital Functional Verification Applications Engineering Department at Siemens EDA

This deeply integrated verification methodology not only accelerates the DFT sign-off process but also transforms verification from passive detection to proactive prevention through AI-driven intelligent analysis, aligning perfectly with the dual demands of high reliability and fast time-to-market in modern chip design.

It is worth noting that Siemens EDA, based on the unified technical foundation of EDA AI System, has deeply integrated AI into every aspect of chip design. In addition to the Questa One intelligent verification software product, there are Calibre Vision AI, Aprisa AI, Solido generative and proxy-based AI, empowering engineers comprehensively to address increasingly complex design challenges.

02.Veloce CSFacilitate the evolution of verification toward full system and multi-scenario environments

In the context of the current surge in chip design complexity, the scope of functional verification has rapidly expanded from the module/IP level to full system and multi-scenario environments. This means that verification work must not only cover full-chip (Full SoC) integration and multi-chiplet collaborative verification but also extend to specific application scenarios, such as automotive systems, encompassing verification of chips, road scenarios, and chassis models. Expanding the boundaries of verification to match real-world application scenarios is key to efficiently exposing system-level risks early and ensuring the functional safety and reliability of chips in complex environments.

To support system-level verification requirements, Siemens EDA Veloce CS supports various interconnect protocols involved in chip design. It fully supports mainstream interconnect standards like UCIe and CXL, as well as cutting-edge interconnect standards including UA Link (Ultra Accelerator), which enables shared DDR and HBM bandwidth between multiple acceleration nodes, and UEC (Ultra Ethernet Consortium) technology based on Virtual Ethernet, meeting the stringent demands for high performance, distributed, and lossless transmission in HPC and AI scenarios.

Meanwhile, as the complexity of heterogeneous integration continues to increase, the associated verification challenges are also intensifying. For instance, the ARM Zena computing subsystem (CSS) integrates up to 16 high-performance Cortex-A720AE CPU clusters to handle the complex workloads of advanced driver-assistance systems (ADAS) and in-vehicle infotainment (IVI); at the same time, its dedicated safety island is powered by the real-time processor Cortex-R82AE, providing ASIL-D level assurance for scenarios with stringent functional safety requirements, making the application scenarios extremely complex. Siemens EDA, through Innexis CodeBench and Veloce Codelink, offers a unified visual debugging environment that effectively addresses the verification needs of such multi-core, multi-vendor heterogeneous systems.

Our toolchain is highly compatible, enabling collaborative processing and deep debugging of multi-core, multi-vendor heterogeneous systems within a single platform without the need to connect multiple hardware debuggers or launch several software suites, thus significantly enhancing verification efficiency and debugging depth.

Chen Zhefei, Application Engineering Manager for Hardware-Assisted Verification Products at Siemens EDA

Notably, on the foundation of supporting various advanced interconnect standards and heterogeneous integrated CPU clusters, Siemens EDA, based on the Veloce Strato CS hardware acceleration platform and the Innexis Developer Pro software environment, has built an end-to-end integrated development process covering virtual models, hybrid models to full RTL levels, which can significantly accelerate the complex SoC design process and support a large number of user cases, especially suitable for efficient collaboration between software and hardware teams. The entire system supports RFRA (Run Fast and Run Accurate), achieving flexible balance between running speed and accuracy: when users focus on development efficiency, it can run in a QEMU virtual environment based on transaction-level models, achieving execution speeds in the hundreds of MHz; when users need to deeply analyze system performance, they can switch to the cycle-accurate Veloce Strato CS hardware acceleration platform to accurately evaluate key metrics such as bandwidth, latency, and power consumption, thereby achieving comprehensive validation and optimization before chip tape-out.

The Veloce platform can effectively reduce tape-out risks. For example, in a customer's design of a general-purpose GPGPU, although its critical PCIe module had already completed simulation verification on other platforms, a deep-seated error that other simulation verification platforms could not capture was only exposed on the Veloce platform through QEMU Host simulating a real server host environment connected via the PIPE interface to the PCIe endpoint. This error was hidden deep within the RTL code and could not be patched through software; if not detected in time, it would have directly led to the failure of core chip functions, causing significant losses.

Chen Zhefei, Application Engineering Manager for Hardware-Assisted Verification Products at Siemens EDA

03. Complete EcosystemComprehensively Boosting Verification Efficiency

Siemens EDA actively constructs a multidimensional and in-depth ecosystem cooperation network. Its cooperation strategy not only covers globally leading high-speed interconnect silicon IP partners but also deeply integrates into mainstream processor architectures and open hardware ecosystems, effectively addressing the verification challenges brought by complex chip and system designs.

In collaboration with core IP partners, Siemens EDA's strategic synergy with Alphawave Semi stands out, introducing the latter’s advanced high-speed interconnect silicon IP to the market through its sales channels, jointly addressing complex interconnection challenges. The products cover Alphawave Semi’s cutting-edge IP platforms for connectivity and memory protocols, such as Ethernet, PCIe, CXL, HBM, and UCIe (die-to-die) interconnects, providing a high-bandwidth, highly reliable interconnect foundation for advanced SoCs, 3D-ICs, and Chiplet architectures.

Our value lies in providing a complete ecosystem chain of 'silicon IP + verification IP.' While clients receive high-performance IP authorization, they can directly utilize a fully verified testing environment that comes with it. This deep integration offers two core advantages: first, it significantly shortens the verification cycle, avoiding the time-consuming process of building a testing platform from scratch; second, it creates a reliable solution that has undergone closed-loop verification, substantially reducing technical risks during the system integration phase and making project timelines more predictable, thereby offering solid support for clients' rapid time-to-market.

Yang Geng, Head of the Digital Functional Verification Applications Engineering Department at Siemens EDA

In terms of processor ecosystem layout, Siemens EDA has adopted a dual-track strategy of 'deepening mainstream' and 'embracing open source,' comprehensively covering diversified computing power demands.

On one hand, the company continues to deepen its long-term strategic partnership with Arm, as its Veloce Strato CS and Veloce proFPGA CS have officially been adopted by Arm as key components of the Arm Neoverse CSS design process; on the other hand, Siemens EDA actively integrates into the RISC-V open ecosystem and closely collaborates with local forces in China. Its Veloce proFPGA CS platform has successfully supported the comprehensive enhancement of verification efficiency for DAMO Academy's high-performance RISC-V processors Xuantie C908X, C920, and C930.

Siemens EDA relies on the AI-powered Questa One intelligent verification platform, the Veloce CS hardware emulation system that supports full-system multi-scenario verification, and a deeply collaborative industry chain ecosystem to build a complete verification solution that spans from IP to system-level, significantly improving verification efficiency and coverage depth. It moves system-level risk identification much earlier in the process, not only providing solid assurance for the successful taping out of complex chips but also substantially shortening the verification cycle, accelerating product time-to-market.

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